1. Field of the Invention
The invention relates in general to a method of forming a non-volatile memory cell, and more particularly to a method of forming a non-volatile memory cell in combination with a chemical mechanical polishing process.
2. Description of the Related Art
The memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), and flash EEPROM. These advanced memory devices can accomplish the tasks that ROM can't do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
The main characteristic of nitride trap memory is dual bit cells having multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. Others store one bit on either side of the cell. The conventional structures and fabricating methods of nitride trap memory cell are described in a lot of articles and references.
Referring to FIG. 1A˜1C, cross-sectional view of diagrams illustrating a conventional method for forming a nitride trap memory. The buried diffusion oxide (BD oxide) 19 is deposited over the substrate 11, on which two gate structures 13 have already formed, as shown in FIG. 1A. These gate structures are covered by a layer 16 of silicon nitride (Si3N4). The thickness of the blocking layer 16 is 1600 angstroms or more,
Next, The whole device is dipped into Hydrofluoric acid (HF) to partially etch the BD oxide away, as shown in FIG. 1B. The BD oxide layer 19b deposited between two gate structures 13 becomes lower than before, and a little peak 19a consisting of BD oxide 19 remains on the silicon nitride layer 16. It is noted that the interface between the BD oxide layer 19b and the gate structure 13 is also exposed to hydrofluoric acid. Weak interface may generate in this step.
Afterward, silicon nitride layer 16 is etched away and the BD oxide peak 19a thereon is also took away, so-called a lift-off process, as shown in FIG. 1C. The substrate is treated with phosphoric acid (H3PO4) of strong causticity for almost one hour, and then the silicon nitride layer 16 would be lift off completely. Phosphoric acid may flow to the substrate 11 along the cracks 20 and etch the substrate 11. Chemical damage on the substrate seriously reduces yield random single bit (RSB) failure rate. Besides, the surface of the BD oxide layer 19c is cupped, and it has to be polished for the following procedures.